In digital logic circuitry, all clocked elements have a minimum specified setup time which defines the required time period which must pass between receipt of data and receipt of a clock signal. The specified setup time varies for different digital devices. Where the data signal is asynchronous to the clock signal, the setup time will usually be violated. If the setup time is violated, then the recipient chip may produce a metastable (i.e., invalid) result. This metastable result can further propagate through the network containing the recipient chip, thereby creating invalid data therethrough.
Under one current solution, the asynchronous data signal is routed through a series of two flip-flops in order to reduce the probability of violation of the setup time. However, this configuration requires an additional two clock periods to move the data through the flip-flops and to the recipient clocked device. Further, there still exists some probability that the setup time will be violated thereby giving rise to a metastable result.
Therefore, a need has arisen for a circuit to eliminate metastable events arising from a data signal asynchronous to a clock signal.